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digital comb filter (ntsc/pal) description the CXD2064Q is an adaptive intra-field comb filter compatible with ntsc and pal systems, and can provide high-precision y/c separation with a single chip. features adaptive intra-field y/c separation m-pal and n-pal supported vertical enhancer horizontal aperture correction 8-bit a/d converter (1-channel) 8-bit d/a converter (2-channel) 4 pll sync tip clamp four 1h delay lines applications y/c separation for color tvs and vcrs structure silicon gate cmos icstructure absolute maximum ratings (ta = 25?, v ss = 0v) supply voltage dv dd v ss ?0.5 to +7.0 v davd v ss ?0.5 to +7.0 v advd v ss ?0.5 to +7.0 v plvd v ss ?0.5 to +7.0 v clvd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage dv dd 5.0 0.25 v davd 5.0 0.25 v advd 5.0 0.25 v plvd 5.0 0.25 v clvd 5.0 0.25 v analog input adin 1.75 vp-p operating temperature topr ?0 to +70 ? ?1 e96x19b91-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2064Q 48 pin qfp (plastic)
? 2 CXD2064Q pin configuration block diagram f i n c k s l p l s l m c k o a d c k c p o p l v s v c v p l v d c l v d c l p e n c l v s d t r p n r v e h 1 v e h 2 v e h 3 m o d 1 d v s s m o d 2 d v d d t e s t v b i r f d v s s t e s t d v d d t e s t t e s t t r a p a p c n d v s s t e s t d v d d n t p l 1 n t p l 2 c l p o a d i n r b a d v s a d v d r t a c o d a v d a y o d a v s v g v r f 2 3 4 5 6 9 1 0 1 1 1 2 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 8 7 a / d c l a m p n t s c : 1 h p a l : 2 h n t s c : 1 h p a l : 2 h l o g i c a l o p e r a t i o n a d a p t i v e f i l t e r o p e r a t i o n d l d / a a d i n d / a c l p o a y o a c o v c o 1 / 4 s w p h a s e c o m p a r a t o r 1 / 2 s w 4 f s c c p o v c v p l s l f i n c k s l v e r t i c a l e n h a n c e m e n t c i r c u i t 2 1 7 9 3 9 3 8 3 7 4 4 4 2
? 3 CXD2064Q pin description clpo adin rb advs advd rt aco davd ayo davs vg vrf irf vb test dv dd dv ss veh3 veh2 veh1 pnr dtr dv dd o i o o o o o i o o i i i i i i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 21 22 23 24 27 internal clamp circuit current output. connect to adin when using the internal clamp. leave this pin open when not in use. comb filter analog input (a/d converter input). reference bottom voltage for the a/d converter (0.52v typ.). a/d converter analog ground. a/d converter analog power supply. (5.0v) reference top voltage for the a/d converter (2.60v typ.). analog chroma signal output. output can be obtained by connecting a resistor between this pin and the analog ground. d/a converter analog power supply. (5.0v) analog luminance signal output. output can be obtained by connecting a resistor between this pin and the analog ground. d/a converter analog ground. d/a converter related pin. connect a capacitor of approximately 0.1 f between this pin and the analog power supply (davd). sets the full-scale value of the y and c-channel d/a converter output signal. connect a resistor of ?6r?(16 times the output resistor ??of the d/a converter). d/a converter related pin. connect to the analog ground (davs) via a capacitor of approximately 0.1 f. test pin. normally fix to ?ow? digital power supply. (5.0v) digital ground. y/c separation mode setting. mod2 mod1 l l adaptive processing mode h l bpf separation mode h h through mode vertical enhancement setting. can be set in 8 stages from veh3 veh2 veh1: lll (off) to hhh (max.) l: ntsc/h: pal, m-pal, n-pal normally fix to ?ow? ntsc/pal/m-pal/n-pal mode setting. ntpl2 ntpl1 l l ntsc l h pal h l m-pal h h n-pal digital power supply. (5.0v) pin no. symbol i/o description 17 19 mod2 mod1 i i 25 26 ntpl2 ntpl1 i i
? 4 CXD2064Q 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 test pin. normally fix to ?ow? digital ground. horizontal aperture correction circuit setting. low: off, high: on. trap filter setting. low: off, high: on. test pin. normally open or fix to ?ow? test pin. normally open or fix to ?ow? digital power supply. (5.0v) test pin. normally open or fix to ?ow? digital ground. clock input. input the burst-locked fsc (2fsc) when using the internal pll. input the burst-locked 4fsc when not using the internal pll. pll control. low: the internal pll is not used. the clock (4fsc) which is input to fin is supplied internally. high: the internal pll is used. vco oscillation output 4fsc clock is supplied internally. selects the clock input to fin. low: fsc, high: 2fsc. when inputting 4fsc to fin (when not using the internal pll), this pin may be set to either ?ow?or ?igh? clock (4fsc) output. clock input for a/d converter. normally connect to mcko. pll phase comparator output. leave open when not using the pll. pll analog ground. vco control voltage input. connect to plvs when not using the pll. pll analog power supply. (5.0v) clamp d/a converter analog power supply. (5.0v) clamp circuit enable pin. low: clamp on, high: clamp off. clamp d/a converter analog ground. pin no. symbol i/o description i i i i i i i i i o i o i i test dv ss apcn trap test test dv dd test dv ss fin cksl plsl mcko adck cpo plvs vcv plvd clvd clpen clvs
? 5 CXD2064Q electrical characteristics dc characteristics (v dd = 4.75 to 5.25v, v ss = 0v, ta = ?0 to +70 c) * 1 all pins * 2 all pins other than * 6 * 3 all input pins other than * 6 * 4 all output pins other than * 5 * 5 cpo (pin 42) * 6 fin (pin 37) * 7 all input pins other than * 8 * 8 pins 32, 33 and 35 * 9 mcko (pin 40) supply voltage 4.75 ?0 vss 0.7v dd 0 v dd ?0.8 0.5 250k ?0 40 3.0 dv dd davd advd plvd clvd topr i dd v i , v o v ih v il t r, t f v oh v ol v in r fb i il , i ih i ih 5.0 90 1m 100 9.0 5.25 +70 v dd 0.3v dd 500 0.4 2.5m 10 240 18.0 v c ma v v ns v vp-p a ns * 1 * 2 * 3 * 1 * 4 * 5 * 4 * 5 * 6 * 7 * 8 * 9 operating temperature supply current input/output voltage input voltage input rise/fall time output voltage clock input amplitude feedback resistance value input leak current clock amplifier output delay clock 18mhz cmos level input i oh = ?ma i oh = ?ma i ol = 4ma i ol = 1.5ma fmax = 50mhz sine wave v in = vss or v dd v in = vss or v dd v ih = v dd applicable pins item symbol measurement conditions min. typ. max. unit
? 6 CXD2064Q i/o pin capacitance (ta = 25 c, f = 1mhz, v in = v out = 0v) internal 8-bit a/d converter characteristics (v dd = 5v, ta = 25 c, f = 10mhz) item input pin capacitance output pin capacitance symbol c in c out min. min. max. 9 11 unit pf item resolution max. conversion speed analog input bandwidth self bias output data delay differential linearity error integral linearity error symbol n fmax bw vrb vrt ?vrb tpd e d e l conditions ?db min. 18 0.48 1.96 ?.0 ?.0 typ. 8 18 0.52 2.08 max. 0.56 2.22 45 +1.0 +2.0 unit bit msps mhz v v ns lsb lsb internal clamp (v dd = 5v, ta = 25 c, f = 10mhz) item clamp level * 1 symbol clv conditions min. typ. 0.67 max. unit v internal 8-bit d/a converter characteristics (v dd = 5v, v rf = 2v, r irf = 3.3k , r = 200 , ta = 25 c, f = 10mhz) item resolution max. conversion speed differential linearity error integral linearity error output full-scale voltage output full-scale current output offset voltage glitch energy conditions r = 75 , 1vp-p output min. 18 ?.8 ?.0 1.805 typ. 8 1.90 9.5 30 max. +0.8 +2.0 1.995 15 1.0 unit bit msps lsb lsb v ma mv pv-s * 1 sync tip clamp symbol n fmax e d e l v fs i fs v os g e
? 7 CXD2064Q description of functions y/c separation mode the y/c separation mode can be switched by the following pin settings. adaptive processing mode: y/c separation is performed by detecting the correlation between three lines and switching between comb filter and bpf processing. bpf separation mode: y/c separation is performed only by bpf processing. through mode: the composite video signal input from adin (pin 2) is a/d converted and then d/a converted without modification. d/a outputs are ayo (pin 9) and aco (pin 7). horizontal aperture correction circuit this circuit corrects the frequency response degradation caused by the aperture effects accompanying d/a conversion. this circuit is valid in the adaptive processing and bpf separation modes noted above. trap filter circuit a trap filter is applied to remove the frequency components near fsc in the luminance signal after y/c separation. this reduces the fsc frequency component gain by approximately 2.5db. this circuit is valid in the adaptive processing and bpf separation modes noted above. using the internal pll (clock selection method) mode name adaptive processing mode bpf separation mode through mode mod2 (pin 17) l h h mod1 (pin 19) l l h pll used pll not used fin (pin 37) fsc input 2fsc input 4fsc input cksl (pin 38) h h l plsl (pin 39) l h l/h
? 8 CXD2064Q vertical enhancement circuit this circuit generates an enhanced component in accordance with the vertical aperture component (luminance difference from the preceding and following lines) of the luminance signal. the vertical aperture of the picture can be enhanced naturally by adding this enhanced component to the luminance signal after y/c separation. the enhancement level can be set in eight steps. the size of | a | in the figure below varies according to the pin settings. accordingly,enhanced level can be changed for portions of natural pictures with small luminance differences where the effects are particularly easy to see. portions with large luminance differences are cut with a limiter so that they are not excessively enhanced. also, portions with extremely large luminance differences such as white and black lines are not enhanced because they need be enhanced any more. 0 a a l i m i t e r l i m i t e r e n h a n c e m e n t l e v e l l u m i n a n c e d i f f e r e n c e off 1 2 3 4 5 6 max | a | large - small pin settings veh3 veh2 veh1 (pin 20) (pin 21) (pin 22) l l l l l h l h l l h h h l l h l h h h l h h h enhancement level
? 9 CXD2064Q application circuit for d/a converter block d a v d d a v s 3 k 2 k 0 . 1 y o u t p u t c o u t p u t 0 . 1 0 . 1 a y o v r f i r f a c o v g v b 0 . 1 1 0 3 . 3 k ( r ) 2 0 0 ( r ) : a n a l o g p o w e r s u p p l y ( 5 v ) : a n a l o g g r o u n d 2 0 0 ( r ) 7 8 9 1 0 1 1 1 2 1 3 1 4 method of selecting the output resistor the CXD2064Q has a built-in current output type d/a converter. to obtain the output voltages, connect resistors to the ayo and aco pins. the specs are as follows: output full-scale voltage v fs = 0.5 to 2.0 [v], output full-scale current i fs = 0 to 15 [ma]. calculate the output resistance value using the relationship v fs = i fs r. in addition, connect a resistor of 16 times the output resistor to the reference current pin (irf). in case this results in a unpractical value, use a resistance value as close to the calculated value as possible. note that, at this time, v fs = v rf 16r/r?(v rf : pin voltage of v rf ). here, r is the resistor connected to ayo/aco, and r?is the resistor connected to irf. power consumption can be reduced by using higher resistance values, but the glitch energy and data settling time increase contrastingly. set the optimum values according to the system applications. v dd , v ss separate the analog and digital systems around the device to reduce the effects of noise. davd is by- passed to davs as close to each other as possible through a ceramic capacitor of approximately 0.1 f. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 10 CXD2064Q external connection diagram h l h l n t p l 1 n t p l 2 f i n c k s l p l s l m c k o a d c k c p o p l v s v c v p l v d c l v d c l p e n c l v s d t r p n r v e h 1 v e h 2 v e h 3 m o d 1 d v s s m o d 2 d v d d t e s t v b i r f d v s s t e s t d v d d t e s t t e s t t r a p a p c n d v s s t e s t d v d d c l p o a d i n r b a d v s a d v d r t a c o d a v d a y o d a v s v g v r f 0 . 1 l 5 6 k 5 6 0 0 . 1 0 . 0 2 2 0 . 1 0 . 1 3 . 3 k 1 0 0 . 1 0 . 1 2 k 3 k 0 . 1 c o u t p u t y o u t p u t 0 . 1 0 . 0 0 1 c o m p o s i t e v i d e o i n p u t 0 . 1 h h l h l l h l h l h l h l h l h l h l h l h 0 . 1 0 . 1 0 . 1 0 . 1 c l o c k i n p u t 2 0 0 2 0 0 : a n a l o g p o w e r s u p p l y ( 5 v ) : a n a l o g g r o u n d h l : c m o s h i g h l e v e l : c m o s l o w l e v e l : d i g i t a l p o w e r s u p p l y ( 5 v ) : d i g i t a l g r o u n d 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 3 4 5 6 7 8 9 1 0 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 11 CXD2064Q notes on operation make the wiring for the signal input to adin (pin 2) as short as possible. also, drive the input signal to adin at low impedance. make the analog and digital power supply and gnd lines as wide and short as possible to ensure low impedance. bypass the analog and digital power supply pins to gnd with a ceramic capacitor of about 0.1 f connected as close to the pin as possible. input a clock that is locked to the burst signal of the input video signal. separate the wiring to the clock input pin fin (pin 37) from the external analog circuits, analog power supplies and analog gnd. adin (analog input signal) set the input signal peak-to-peak value vpp to 1.75v or less. additionally, vpp is recommended to be 1.3v or more since the a/d converter input dynamic range should be made as large as possible. the dc level at the adin pin is as shown in the diagram above when the internal sync tip clamp is used. labeling the internal d/a converter ayo output full-scale voltage as vfs, the correspondence between the adin pin voltage and ayo output pin voltage (dc level) is as follows; dc voltage at point b ? ayo maximum output voltage [v] dc voltage at point a ? 0 [v] dc voltage at point c ? vfs [v] the vfs is the ayo output voltage generated when the voltage equivalent to the point c is input. internal delay the delay from the internal a/d converter to the d/a converter output is as follows; ntsc: 1h + 24.5 clocks + a ns pal: 2h + 24.5 clocks + a ns ( a : d/a converter analog output delay = approximately 20ns) the 24.5 clocks are the sum of the clocks shown below; a/d converter: 3.5 clocks (?.5?is for fetching the data at the fall of the clock.) internal logic: 20 clocks d/a converter: 1 clock c ? b ? a ? v p p 2 . 6 0 v ( r e f e r e n c e t o p v o l t a g e t y p i c a l v a l u e f o r i n t e r n a l a / d c o n v e r t e r ) 0 . 6 7 v ( s y n c t i p c l a m p l e v e l ) 0 . 5 2 v ( r e f e r e n c e b o t t o m v o l t a g e t y p i c a l v a l u e f o r i n t e r n a l a / d c o n v e r t e r )
? 12 CXD2064Q application circuit 1 fsc is used for clock h l h l n t p l 1 n t p l 2 f i n c k s l p l s l m c k o a d c k c p o p l v s v c v p l v d c l v d c l p e n c l v s d t r p n r v e h 1 v e h 2 v e h 3 m o d 1 d v s s m o d 2 d v d d t e s t v b i r f d v s s t e s t d v d d t e s t t e s t t r a p a p c n d v s s t e s t d v d d c l p o a d i n r b a d v s a d v d r t a c o d a v d a y o d a v s v g v r f 0 . 1 l 5 6 k 5 6 0 0 . 1 0 . 0 2 2 0 . 1 0 . 1 3 . 3 k 1 0 0 . 1 0 . 1 2 0 0 2 k 3 k 0 . 1 c o u t p u t y o u t p u t 0 . 1 0 . 0 0 1 c o m p o s i t e v i d e o i n p u t h l h l 0 . 1 h l h l h l h l h l h l h l h l h l h l p f b u r s t - l o c k e d c l o c k ( f s c ) x t a l p a l : 4 . 4 3 m h z n t s c : 3 . 5 8 m h z 0 . 1 0 . 1 0 . 1 0 . 1 l p f 2 0 0 l p f h l c l o c k g e n e r a t o r : a n a l o g p o w e r s u p p l y ( 5 v ) : a n a l o g g r o u n d : d i g i t a l g r o u n d : d i g i t a l p o w e r s u p p l y ( 5 v ) : c m o s h i g h l e v e l : c m o s l o w l e v e l 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 3 4 5 6 7 8 9 1 0 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 13 CXD2064Q application circuit 2 2fsc is used for clock h l h l n t p l 1 n t p l 2 f i n c k s l p l s l m c k o a d c k c p o p l v s v c v p l v d c l v d c l p e n c l v s d t r p n r v e h 1 v e h 2 v e h 3 m o d 1 d v s s m o d 2 d v d d t e s t v b i r f d v s s t e s t d v d d t e s t t e s t t r a p a p c n d v s s t e s t d v d d c l p o a d i n r b a d v s a d v d r t a c o d a v d a y o d a v s v g v r f 0 . 1 l 5 6 k 5 6 0 0 . 1 0 . 0 2 2 0 . 1 0 . 1 3 . 3 k 1 0 0 . 1 0 . 1 2 0 0 2 k 3 k 0 . 1 c o u t p u t y o u t p u t 0 . 1 0 . 0 0 1 c o m p o s i t e v i d e o i n p u t h l h l 0 . 1 h l h l h l h l h l h l h l h l h l h l p f c l o c k g e n e r a t o r b u r s t - l o c k e d c l o c k ( 2 f s c ) x t a l p a l : 8 . 8 6 m h z n t s c : 7 . 1 6 m h z 0 . 1 0 . 1 0 . 1 0 . 1 l p f 2 0 0 l p f h l : a n a l o g p o w e r s u p p l y ( 5 v ) : a n a l o g g r o u n d : d i g i t a l p o w e r s u p p l y ( 5 v ) : d i g i t a l g r o u n d : c m o s h i g h l e v e l : c m o s l o w l e v e l 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 3 4 5 6 7 8 9 1 0 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 14 CXD2064Q application circuit 3 4fsc is used for clock h l h l f i n c k s l p l s l m c k o a d c k c p o p l v s v c v p l v d c l v d c l p e n c l v s d t r p n r v e h 1 v e h 2 v e h 3 m o d 1 d v s s m o d 2 d v d d t e s t v b i r f d v s s t e s t d v d d t e s t t e s t t r a p a p c n d v s s t e s t d v d d n t p l 1 n t p l 2 c l p o a d i n r b a d v s a d v d r t a c o d a v d a y o d a v s v g v r f 0 . 1 l 0 . 1 0 . 1 0 . 1 3 . 3 k 1 0 0 . 1 0 . 1 2 0 0 2 k 3 k 0 . 1 c o u t p u t y o u t p u t 0 . 1 0 . 0 0 1 c o m p o s i t e v i d e o i n p u t h l h l 0 . 1 h l h l h l h l h l h l h l h l h l h l p f c l o c k g e n e r a t o r b u r s t - l o c k e d c l o c k ( 4 f s c ) x t a l p a l : 1 7 . 7 m h z n t s c : 1 4 . 3 m h z 0 . 1 0 . 1 0 . 1 0 . 1 l p f 2 0 0 l p f h l : a n a l o g p o w e r s u p p l y ( 5 v ) : a n a l o g g r o u n d : d i g i t a l p o w e r s u p p l y ( 5 v ) : d i g i t a l g r o u n d : c m o s h i g h l e v e l : c m o s l o w l e v e l 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 3 4 5 6 7 8 9 1 0 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 15 CXD2064Q s o n y c o d e e i a j c o d e j e d e c c o d e m p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m p l a t i n g 4 2 / c o p p e r a l l o y 4 8 p i n q f p ( p l a s t i c ) 1 5 . 3 0 . 4 1 2 . 0 0 . 1 + 0 . 4 0 . 8 0 . 3 0 . 1 + 0 . 1 5 0 . 2 4 1 3 2 4 2 5 3 6 3 7 4 8 1 1 2 2 . 2 0 . 1 5 + 0 . 3 5 0 . 9 0 . 2 0 . 1 0 . 1 + 0 . 2 1 3 . 5 0 . 1 5 0 . 0 5 + 0 . 1 q f p - 4 8 p - l 0 4 q f p 0 4 8 - p - 1 2 1 2 0 . 7 g 0 . 1 5 package outline unit : mm

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